The present invention generally relates to delay line devices and more particularly to a distributed constant type delay line device and a manufacturing method thereof.
In digital processing systems such as telecommunication systems and computers in which processing of digital signals is performed, a distributed constant type delay line device is used for timing adjustment of the signals or adjustment of delay time of the signal so that the digital signals passed through various components and wiring patterns have a proper timing.
The distributed constant type delay line device is a device comprising a plate-like base body carrying a delay path pattern on one side for delaying the signal passing therethrough. When the delay time to be obtained by such a device exceeds about 2 nanoseconds, however, ordinary sized delay line device is not appropriate for the purpose, as the device cannot produce such a large delay time. Thus, the delay line device is constructed by assembling two base bodies respectively carrying delay line patterns so that a long delay path is formed.
FIGS. 1 and 2 show a prior art delay line device 10 using two base bodies. Referring to the drawings, the device 10 comprises a first base body 14 printed with a conductor pattern 12 which in turn comprises a pair of zigzag conductor patterns 12a and 12b as shown in FIG. 1 and a second base body 17 printed with another zigzag conductor pattern 15. The conductor pattern 12a and the conductor pattern 12b are provided on a front side of the first base body 14 and are formed symmetrically about a center line (not shown) passing centrally through the body 14. On the other hand, the conductor pattern 15 is a single pattern formed also symmetrically on a front side of the second base body 17. Further, the base bodies 14 and 17 carry conductor layers 14a and 17a on respective rear sides for ground connection and are assembled as a unitary body by connecting the conductive layers as shown in FIG. 3 by soldering or glueing using a conductive adhesive.
As can be seen from FIGS. 1 and 2, the base body 14 has a length L.sub.1 and a width W.sub.1 and the base body 17 has a length L.sub.2 and a width W.sub.2, in which the width W.sub.1 is made substantially larger than the width W.sub.2. On the other hand, the length L.sub.1 and the length L.sub.2 are made identical. In the delay line device 10 having such a construction, a pair of connection pins 20 and 21 are provided on a bottom edge of the base body 14 and are connected to respective first ends of the conductor patterns 12a and 12b. Further, respective second ends of the conductor patterns 12a and 12b are connected to ends of the conductor pattern 15 by jumpers 18 and 19 as shown in FIGS. 1 and 2. Furthermore, ground pins 22 and 23 are provided on the bottom edge of the base body 14 in contact with the conductor layer 14a as shown in FIG. 2. In order to avoid contact between the conductor layer 14a and the pins 20 and 21, there is provided a cutout region 14b in the conductor layer 14a along the bottom edge of the body 14 for avoiding the pins 20 and 21.
Thus, an input signal applied to the pin 20 is passed through the conductor 12a, conductor 15 and the conductor 12b and reaches the pin 21 with a delay time proportional to the distance of the delay path extending from the pin 20 to the pin 21.
In such a prior art delay line device, there is a problem in that the obtained delay time is limited due to the limited size of the second base body 17 having the width W.sub.2 which is substantially reduced with respect to the width W.sub.1 of the first base body 14. Such a difference in size of the base body is needed for securing region for connection of the pins 20 -23 at the bottom edge of the base body 14. When the second base body 17 is designed to have a same size as that of the base body 14, there would be no place for providing the pins 20 and 21 for input and output of the signals and particularly for the pins 22 and 23 for ground connection as the conductor layer 14a or 17a is fully embedded in the base bodies. Thus, the conventional delay line device inevitably has to be designed to use two different base bodies having different sizes which, however, inevitably invites increase in size of the device when a large delay time is needed. However, such an increase in the size of the device is undesirable from the view point of reducing the size of the apparatus using the delay line device.
Further, such a prior art delay line device has a problem in manufacturing because of the difference in the size of the base body 14 and the base body 17. Thus, when the base body 14 and the base body 17 are obtained by cutting of a large board, one has to provide two separate boards, one for the base body 14 and the other for the base body 17, as the cutting of a single board into the body 14 and body 17 having different sizes and shapes needs an extremely complex sawing operation. Associated with the use of different base bodies 14 and 17, there is another problem in that the conductor patterns 12 for the base body 14 and the conductor pattern 15 for the base body 17 have to be provided separately. Such a separately performed patterning increases the number of manufacturing steps and hence the cost of the device.
Further, the prior art delay line device has another problem in that two jumpers 18 and 19 have to be used for connecting the conductor pattern 12 to the conductor pattern 15. Such a use of two jumpers increases the risk that the connection is failed and thus reduces the reliability of the device. Needless to say, the manufacturing step is increased by using two jumpers as compared to the case where no or single jumper is used.
In the prior art delay line device, there is still another problem in that the conductor layer 14a provided on the rear side of the base body 14 has to be patterned such that the conductor layer 14a avoids the vicinity of the pins 20 and 21. Such patterning of the conductor layer 14a obviously decreases the efficiency of production of the device.
Furthermore, the prior art device carries both the pin 20 for inputting the signal and the pin 21 for outputting the signal on the base body 14. In other words, there is a forward path comprising the conductor pattern 12a and a left half of the conductor pattern 15 for passing the input signal applied to the input terminal 20 towards the interior of the device and a return path comprising a right half of the conductor pattern 15 and the conductor patter 12a for passing the signal to the output terminal 21. Thus, it is inevitable that the conductor patterns 12 and 15 are turned a number of times for a predetermined length of the delay path. When such a turn or bend is made in the conductor pattern, there is an increase in the inductance which may cause undesirable impedance change in combination with capacitance underneath the conductor pattern.